大聯盟計畫歷年來重要成果

IEDM論文

編號 姓名(中文部分僅列本計畫PIs/Co-PIs姓名) 會議論文名稱 國際會議名稱、舉辦時間、發表日期
19 Yu-Shiang Huang, Chung-En Tsai, Chien-Te Tu, Hung-Yu Ye, Yi-Chun Liu, Fang-Liang Lu, and C. W. Liu (劉致為) First Stacked Ge0.88Sn0.12 pGAAFETs with Cap, LG=40nm, Compressive Strain of 3.3%, and High S/D Doping by CVD Epitaxy Featuring Record ION of 58A at VOV=VDS= -0.5V, Record Gm,max of 172S at VDS= -0.5V, and Low Noise 2019 IEEE International Electron Devices Meeting (IEDM), December 7-11, 2019
18 Chien-Te Tu, Yu-Shiang Huang, Fang-Liang Lu, Hsiao-Hsuan Liu, Chung-Yi Lin, Yi-Chun Liu, and C. W. Liu (劉致為) First Vertically Stacked Tensily Strained Ge0.98Si0.02 nGAAFETs with No Parasitic Channel and LG = 40 nm Featuring Record ION = 48 A at VOV=VDS=0.5V and Record Gm,max (S/m)/SSSAT(mV/dec) = 8.3 at VDS=0.5V/ 2019 IEEE International Electron Devices Meeting (IEDM), December 7-11, 2019
17 M. H. Lee (李敏鴻), K.-T. Chen, C.-Y. Liao, G.-Y. Siang, C. Lo, H.-Y. Chen, Y.-J. Tseng, C.-Y. Chueh, C. Chang, Y.-Y. Lin, Y.-J. Yang, F.-C. Hsieh, S. T. Chang, M.-H. Liao, K.-S. Li, and C. W. Liu (劉致為) Bi-directional Sub-60mV/dec, Hysteresis-Free, Reducing Onset Voltage and High Speed Response of Ferroelectric-AntiFerroelectric Hf0.25Zr0.75O2 Negative Capacitance FETs 2019 IEEE International Electron Devices Meeting (IEDM), December 7-11, 2019
16 Y.D. Lin, H.Y. Lee, Y.T. Tang, P.C. Yeh, H.Y. Yang, P.S. Yeh, C.Y. Wang, J.W. Su, S.H. Li, S.S. Sheu, T.H. Hou, W.C. Lo, M. H. Lee (李敏鴻), M.F. Chang, Y.C. King and C.J. Lin 3D Scalable, Wake-up Free, and Highly Reliable FRAM Technology with Stress-Engineered HfZrOx 2019 IEEE International Electron Devices Meeting (IEDM) December 7-11, 2019
15 Ya-Jui Tsou, Chia-Che Chung, Jih-Chao Chiu, Huan-Chi Shih, and C. W. Liu (劉致為) Thermal and Reliability Modeling of FinFET-Driven STT-pMTJ Array Considering Mutual Coupling, 3D Heat Flow, and BEOL Effects *poster 2019 IEEE International Electron Devices Meeting (IEDM), December 7-11, 2019
14 M. H. Lee (李敏鴻), K.-T. Chen, C.-Y. Liao, S.-S. Gu, G.-Y. Siang, Y.-C. Chou, H.-Y. Chen, J. Le, R.-C. Hong, Z.-Y. Wang, S.-Y. Chen, P.-G. Chen, M. Tang, Y.-D. Lin, H.-Y. Lee, K.-S. Li, and C. W. Liu (劉致為) Extremely Steep Switch of Negative-Capacitance Nanosheet GAA-FETs and FinFETs 2018 International Electron Devices Meeting (IEDM), December 1-5, 2018
13 Kai-Shin Li, Yun-Jie Wei, Yi-Ju Chen, Wen-Cheng Chiu, Hsiu-Chih Chen, Min-Hung Lee (李敏鴻), Yu-Fan Chiu, Fu-Kuo Hsueh, Bo-Wei Wu, Pin-Guang Chen, Tung-Yan Lai, Chun-Chi Chen, Jia-Min Shieh (謝嘉民), Wen-Kuan Yeh (葉文冠), Sayeef Salahuddin, Chenming Hu Negative-Capacitance FinFET Inverter, Ring Oscillator 2018 International Electron Devices Meeting (IEDM), December 1-5, 2018
12 Ya-Jui Tsou, Zong-You Luo, Chia-Che Chung, and C. W. Liu (劉致為) Thermal Modeling of FinFET-Driven Spin-Orbit Torque MRAM Considering Thermal Coupling and BEOL Effects*poster 2018 International Electron Devices Meeting (IEDM) December 1-5, 2018
11 M. H. Lee (李敏鴻), P.-G. Chen, S.-T. Fan, Y.-C. Chou, C.-Y. Kuo, C.-H. Tang, H.-H. Chen, S.-S. Gu, R.-C. Hong, Z.-Y. Wang, S.-Y. Chen, C.-Y. Liao, K.-T. Chen, S. T. Chang (張書通), M.-H. Liao, K.-S. Li, and C. W. Liu (劉致為) Ferroelectric Al:HfO2 Negative Capacitance FETs 2017 International Electron Devices Meeting (IEDM) December 2-6, 2017
10 Yu-Shiang Huang, Fang-Liang Lu, Ya-Jui Tsou, Chung-En Tsai, Chung-Yi Lin, Chih-Hao Huang, and C. W. Liu (劉致為) First Vertically Stacked GeSn Nanowire pGAAFETs with Ion=1850A/m (VOV=VDS=-1V) on Si by GeSn/Ge CVD Epitaxial Growth and Optimum Selective Etching 2017 International Electron Devices Meeting (IEDM), December 2-6, 2017
9 Vita Pi-Ho Hu (胡璧合), Pin-Chieh Chiu, Angada B. Sachid, Chenming Hu Negative Capacitance Enables FinFET and FDSOI Scaling to 2 nm Node 2017 International Electron Devices Meeting (IEDM), December 2-6, 2017
8 M. H. Lee (李敏鴻), S.-T. Fan , C.-H. Tang , P.-G. Chen, Y.-C. Chou , H.-H. Chen , J.-Y. Kuo , M.-J. Xie, S.-N. Liu , M.-H. Liao , C.-A. Jong , K.-S. Li , M.-C. Chen , and C. W. Liu (劉致為) Physical Thickness 1.x nm Ferroelectric HfZrOx Negative Capacitance FETs 2016 International Electron Devices Meeting (IEDM), Dec. 3-7, 2016
7 I-Hsieh Wong, Fang-Liang Lu, Shih-Hsien Huang, Hung-Yu Ye, Chun-Ti Lu, Jhih-Yang Yan, Yu-Cheng Shen, Yu-Jiun Peng, Huang-Siang Lan, and C. W. Liu (劉致為) High Performance Ge Junctionless Gate-all-around NFETs with Simultaneous Ion =1235 A/m at VOV=VDS=1V, SS=95 mV/dec, high Ion/Ioff=2E6, and Reduced Noise Power Density using S/D Dopant Recovery by Selective Laser Annealin 2016 International Electron Devices Meeting (IEDM), Dec. 3-7, 2016
6 Yu-Shiang Huang, Chih-Hsiung Huang, Fang-Liang Lu, Chung-Yi Lin, Hung-Yu Ye, I-Hsieh Wong, Sun-Rong Jan, Huang-Siang Lan, C. W. Liu (劉致為), Yi-Chiau Huang, Hua Chung, Chorng-Ping Chang, Schubert S. Chu, and Satheesh Kuppurao Record High Mobility (428cm2/V-s) of CVD-grown Ge/Strained Ge0.91Sn0.09 /Ge Quantum Well p-MOSFETs 2016 International Electron Devices Meeting (IEDM), Dec. 3-7, 2016
5 Jhih-Yang Yan, Sun-Rong Jan, Yu-Jiun Peng, H. H. Lin, W. K. Wan, Y.-H. Huang, Bigchoug Hung, K.-T. Chan, Michael Huang, M.-T. Yang and C. W. Liu (劉致為) Thermal Resistance Modeling of Back-end Interconnect and Intrinsic FinFETs, and Transient Simulation of Inverters with Capacitive Loading Effects 2016 International Electron Devices Meeting (IEDM) Dec. 3-7, 2016
4 M. H. Lee (李敏鴻), P.-G. Chen, C. Liu, K-Y. Chu, C.-C. Cheng, M.-J. Xie, S.-N. Liu, J.-W. Lee, S.-J. Huang, M.-H. Liao, M. Tang, K.-S. Li and M.-C. Chen Prospects for Ferroelectric HfZrOx FETs Experiment with CET=0.98nm, SSfor=42mV/dec, SSrev=28mV/dec, Turn-off <0.2V, and Hysteresis-Free Strategies 2015 International Electron Devices Meeting (IEDM), Dec. 7-9, 2015
3 K. S. Li, P.-G. Chen, T. Y. Lai, C. H. Lin, C.-C. Cheng, C. C. Chen, M.-H. Liao, M. H. Lee (李敏鴻), M. C. Chen, J. M. Sheih (謝嘉民), W. K. Yeh (葉文冠), F. L. Yang, Sayeef Salahuddin, Chenming Hu Sub-60mV-Swing Negative-Capacitance FinFET without Hysteresis 2015 International Electron Devices Meeting (IEDM), Dec. 7-9, 2015
2 I-Hsieh Wong, Yen-Ting Chen, Shih-Hsien Huang, Wen-Hsien Tu, Yu-Sheng Chen, Tai-Cheng Shieh, Tzu-Yao Lin, Huang-Siang Lan, and C. W. Liu (劉致為) In-situ Doped and Tensily Stained Ge Junctionless Gate-all-around nFETs on SOI Featuring Ion = 828 uA/um, Ion/Ioff ~ 1E5, DIBL= 16-54 mV/V, and 1.4X External Strain Enhancement 2014 International Electron Devices Meeting (IEDM), Dec. 15-17, 2014
1 M. H. Lee (李敏鴻), J.-C. Lin, Y.-T. Wei, C.-W. Chen, W.-H. Tu, H.-K. Zhuang, M. Tang Ferroelectric Negative Capacitance Hetero-Tunnel Field-Effect-Transistors with Internal Voltage Amplification 2013 IEEE International Electron Devices Meeting (IEDM), Dec. 9-11, 2013

VLSI論文

編號 姓名(中文部分僅列本計畫PIs/Co-PIs姓名) 會議論文名稱 國際會議名稱、舉辦時間、發表日期
6 Fang-Liang Lu, Chung-En Tsai, Chih-Hsiung Huang, Hung-Yu Ye, Shih-Ya Lin, and C. W. Liu (劉致為) Record Low Contact Resistivity (4.4x10-10Ω-cm2) to Ge Using In-situ B and Sn Incorporation by CVD With Low Thermal Budget (≤400℃) and Without Ga 2019 Symposium on VLSI Technology (VLSI-Technology) (June 9-14, 2019)9
5 Yu-Shiang Huang, Hung-Yu Ye, Fang-Liang Lu, Yi-Chun Liu, Chien-Te Tu, Chung-Yi Lin, Shih-Ya Lin, Sun-Rong Jan, and C. W. Liu (劉致為) First Vertically Stacked, Compressively Strained, and Triangular Ge0.91Sn0.09 pGAAFETs with High ION of 19.3uA at VOV=VDS=-0.5V, Gm of 50.2uS at VDS=-0.5V and Low SSlin of 84mV/dec by CVD Epitaxy and Orientation Dependent Etching 2019 Symposium on VLSI Technology (VLSI-Technology) (June 9-14, 2019)
4 Jhih-Yang Yan, Chia-Che Chung, Sun-Rong Jan, H. H. Lin, W. K. Wan, M.-T. Yang, C. W. Liu (劉致為) Comprehensive Thermal SPICE Modeling of FinFETs and BEOL with Layout Flexibility Considering Frequency Dependent Thermal Time Constant, 3D Heat Flows, Boundary/Alloy Scattering, and Interfacial Thermal Resistance with Circuit Level Reliability Evaluation 2018 Symposium on VLSI Technology (VLSI-Technology) (June 18-22, 2018)
3 Y.-C. Chiu, C.-H. Cheng, C.-Y. Chang, M.-H. Lee(李敏鴻), H.-H. Hsu and S.-S. Yen Low Power 1T DRAM/NVM Versatile Memory Featuring Steep Sub-60-mV/decade Operation, Fast 20-ns Speed, and Robust 85C-Extrapolated 1016 Endurance 2015 Symposia on VLSI Technology and Circuits (June 15-19, 2015)
2 M.-H. Liao (廖洺漢), P. G. Chen, S. C. Huang, S. C. Kao, C. X. Hung, K. H. Liu, C. Lien, C. Y. Liu The demonstration of D-SMT stressor on Si and Ge n-FinFETs 2014 Symposia onVLSI Technology and Circuits (June 9-13, 2014)
1 M. Liao (廖洺漢), S. C. Huang, C. Y. Liu, P. G. Chen, S. C. Kao, C. Lien The demonstration of colossal magneto-capacitance and “negative” capacitance effect with the promising characteristics of Jg-EOT and transistor’s performance on Ge (100) n-FETs by the novel magnetic gate stack scheme design 2014 Symposia onVLSI Technology and Circuits (June 9-13, 2014)