| 1 | 3D Stackable Vertical Ferroelectric Tunneling Junction (V-FTJ) with on/off Ratio 1500x, Applicable Cell Current, Self-Rectifying Ratio 1000x, Robust Endurance of 109 Cycles, Multilevel and Demonstrated Macro Operation Toward High-Density BEOL NVMs | J.-Y. Lee, F.-S. Chang, K.-Y. Hsiang, P.-H. Chen, Z.-F. Luo, Z.-X. Li, J.-H. Tsai, C. W. Liu (劉致為), and M. H. Lee(李敏鴻) | 2023 Symposium on VLSI Technology and Circuits (VLSI) | |
| 2 | FeRAM Recovery up to 200 Periods with Accumulated Endurance 1012 Cycles and an Applicable Array Circuit toward Unlimited eNVM Operations | K.-Y. Hsiang, J.-Y. Lee, F.-S. Chang, Z.-F. Lou, Z.-X. Li, Z.-H. Li, J.-H. Chen, C. W. Liu, T.-H. Hou, and M. H. Lee (李敏鴻) | 2023 Symposium on VLSI Technology and Circuits (VLSI) | |
| 3 | Extremely High-k Hf0.2Zr0.8O2 Gate Stacks Integrated into Ge0.95Si0.05 Nanowire and Nanosheet nFETs Featuring Respective Record ION per Footprint of 9200μA/μm and Record ION per Stack of 360μA at VOV=VDS=0.5V | Yi-Chun Liu, Yu-Rui Chen, Yun-Wen Chen, Hsin-Cheng Lin, Wan-Hsuan Hsieh, Chien-Te Tu, Bo-Wei Huang, Wei-Jen Chen, Chun-Yi Cheng, Shee-Jier Chueh, and C. W. Liu (劉致為) | 2023 Symposium on VLSI Technology and Circuits (VLSI) | |
| 4 | First Stacked Nanosheet FeFET Featuring Memory Window of 1.8V at Record Low Write Voltage of 2V and Endurance >1E11 Cycles | Yu-Rui Chen, Yi-Chun Liu, Zefu Zhao, Wan-Hsuan Hsieh, Jia-Yang Lee, Chien-Te Tu, Bo-Wei Huang, Jer-Fu Wang, Shee-Jier Chueh, Yifan Xing, Guan-Hua Chen, Hung-Chun Chou, Dong Soo Woo, M. H. Lee, and C. W. Liu (劉致為) | 2023 Symposium on VLSI Technology and Circuits (VLSI) | |
| 5 | Towards Epitaxial Ferroelectric HZO on n+-Si/Ge Substrates Achieving Record 2Pr = 84 μC/cm2 and Endurance > 1E11 | Zefu Zhao, Yu-Rui Chen, Yun-Wen Chen, Wan-Hsuan Hsieh, Jer-Fu Wang, Jia-Yang Lee, Yifan Xing, Guan-Hua Chen, and C. W. Liu (劉致為) | 2023 Symposium on VLSI Technology and Circuits (VLSI) | |
| 6 | First Demonstration of a-IGZO GAA Nanosheet FETs Featuring Achievable SS=61 mV/dec, Ioff<10-7mA/mm, DIBL=44 mV/V, Positive VT, and Process Temp. of 300 oC | Jih-Chao Chiu, Eknath Sarkar, Yuan-Ming Liu, Yu-Ciao Chen, Yu-Cheng Fan, and C. W. Liu (劉致為) | 2023 Symposium on VLSI Technology and Circuits (VLSI) | |
| 7 | Energy- and Area-Efficient 8T SRAM Cell with FEOL CFETs and BEOL-Compatible Transistors | M. Lee, Z.-Y. Huang, S.-F. Fang, Y.-C. Lu, and V. P.-H. Hu (胡璧合) | 2022 IEEE International Electron Devices Meeting (IEDM) | |
| 8 | First Demonstration of Monolithic 3D Self-aligned GeSi Channel and Common Gate Complementary FETs by CVD Epitaxy Using Multiple P/N Junction Isolation | Chien-Te Tu, Yi-Chun Liu, Bo-Wei Huang, Yu-Rui Chen, Wan-Hsuan Hsieh, Chung-En Tsai, Shee-Jier Chueh, Chun-Yi Cheng, Yichen Ma, and C. W. Liu (劉致為) | 2022 IEEE International Electron Devices Meeting (IEDM) | |
| 9 | Novel Opposite Polarity Cycling Recovery (OPCR) of HfZrO2 Antiferroelectric-RAM with an Access Scheme Toward Unlimited Endurance | K.-Y. Hsiang, Y.-C. Chen, F.-S. Chang, C.-Y. Lin, C.-Y. Liao, Z.-F. Lou, J.-Y. Lee, W.-C. Ray, Z.-X. Li, C.-C. Wang, H.-C. Tseng, P.-H. Chen, J.-H. Tsai, M. H. Liao, T.-H. Hou, C. W. Liu (劉致為), P.-T. Huang, P. Su, and M. H. Lee (李敏鴻) | 2022 IEEE International Electron Devices Meeting (IEDM) | |
| 10 | Superlattice HfO2-ZrO2 based Ferro-Stack HfZrO2 FeFETs: Homogeneous-Domain Merits Ultra-Low Error, Low Programming Voltage 4 V and Robust Endurance 109 cycles for Multibit NVM | C.-Y. Liao, Z.-F. Lou, C.-Y. Lin, A. Senapati, R. Karmakar, K.-Y. Hsiang, Z.-X. Li, W.-C. Ray, J.-Y. Lee, P.-H. Chen, F.-S. Chang, H.-H. Tseng, C.-C. Wang, J.-H. Tsai, Y.-T. Tang, S. T. Chang (張書通), C. W. Liu (劉致為), S. Maikap (麥凱), and M. H. Lee (李敏鴻) | 2022 IEEE International Electron Devices Meeting (IEDM) | |
| 11 | Interfacial-Layer Design for Hf1-xZrxO2-Based FTJ Devices: From Atom to Array | H.-L. Chiang, J.-F. Wang, K.-H. Lin, C.-H. Nien, J.-J. Wu, K.-Y. Hsiang, C.-P. Chuu, Y.-W. Chen, X.W. Zhang, C. W. Liu (劉致為), Tahui Wang, C.-C. Wang, M.-H. Lee (李敏鴻), M.-F. Chang, C.-S. Chang, and T.C. Chen | 2022 Symposia on VLSI Technology and Circuits (VLSI) | |
| 12 | Nearly Ideal Subthreshold Swing and Delay Reduction of Stacked Nanosheets Using Ultrathin Bodies | Chung-En Tsai, Chun-Yi Cheng, Bo-Wei Huang, Hsin-Cheng Lin, Tao Chou, Chien-Te Tu, Yi-Chun Liu, Sun-Rong Jan, Yu-Rui Chen, Wan-Hsuan Hsieh, Kung-Ying Chiu, Shee-Jier Chueh, and C. W. Liu (劉致為) | 2022 Symposia on VLSI Technology and Circuits (VLSI) | |
| 13 | Endurance > 1011 Cycling of 3D GAA Nanosheet Ferroelectric FET with Stacked HfZrO2 to Homogenize Corner Field Toward Mitigate Dead Zone for High-Density eNVM | C.-Y. Liao, K.-Y. Hsiang, Z.-F. Lou, H.-C. Tseng, C.-Y. Lin, Z.-X. Li, F.-C. Hsieh, C.-C. Wang, F.-S. Chang, W.-C. Ray, Y.-Y. Tseng, S. T. Chang, T.-C. Chen, and M. H. Lee (李敏鴻) | 2022 Symposia on VLSI Technology and Circuits (VLSI) | |
| 14 | High-Density and High-Speed 4T FinFET SRAM for Cryogenic Computing | V. P.-H. Hu (胡璧合), Chang-Ju Liu, Hung-Li Chiang, Jer-Fu Wang, Chao-Ching Cheng, Tzu-Chiang Chen, and Meng-Fan Chang | 2021 IEEE International Electron Devices Meeting (IEDM) | |
| 15 | Contact Engineering for High-Performance N-Type 2D Semiconductor Transistors | Y. Lin, P.-C. Shen, C. Su, A.-S. Chou, T. Wu, C.-C. Cheng, J.-H. Park, M.-H. Chiu, A.-Y. Lu, H.-L. Tang, M. M. Tavakoli, G. Pitner, X. Ji, C. McGahan, X. Wang, Z. Cai, N. Mao, J. Wang, Y. Wang, W. Tisdale, X. Ling, K. E. Aidala, V. Tung, J. Li1 , A. Zettl, C.-I. Wu(吳志毅), Jing Guo, H. Wang, J. Bokor, T. Palacios, L.-J. Li , J. Kong | 2021 IEEE International Electron Devices Meeting (IEDM) | |
| 16 | Antimony Semimetal Contact with Enhanced Thermal Stability for High Performance 2DElectronics, | A-S Chou, T. Wu, C-C Cheng, S-S Zhan, I-C Ni, S-Y Wang, Y-C Chang, S-L Liew,E.Chen, W-H Chang, C-I Wu (吳志毅), J. Cai, H.-S. Philip Wong and H. Wang | 2021 IEEE International Electron Devices Meeting (IEDM) | |
| 17 | Highly Stacked 8 Ge0.9Sn0.1 Nanosheet pFETs with Ultrathin Bodies (~3nm) and Thick Bodies (~30nm) Featuring the Respective Record ION/IOFF of 1.4x107 and Record ION of 92μA at VOV=VDS= -0.5V by CVD Epitaxy and Dry Etching | Chung-En Tsai, Yi-Chun Liu, Chien-Te Tu, Bo-Wei Huang, Sun-Rong Jan, Yu-Rui Chen, Jyun-Yan Chen, Shee-Jier Chueh, Chun-Yi Cheng, Chia-Jung Tsen, Yichen Ma, and C. W. Liu (劉致為) | 2021 IEEE International Electron Devices Meeting (IEDM) | |
| 18 | First Demonstration of Interface-Enhanced SAF Enabling 400oC-Robust 42 nm p-SOT-MTJ Cells with STT-Assisted Field-Free Switching and Composite Channels | Ya-Jui Tsou, Kai-Shin Li, Jia-Min Shieh, Wei-Jen Chen, Hsiu-Chih Chen, Yi-Ju Chen, Cho-Lun Hsu, Yao-Min Huang, Fu-Kuo Hsueh, Wen-Hsien Huang, Wen-Kuan Yeh, Huan-Chi Shih, Pang-Chun Liu, C. W. Liu (劉致為), Yu-Shen Yen, Chih-Huang Lai, Jeng-Hua Wei, Denny D. Tang, and Jack Yuan-Chen Sun | 2021 Symposium on VLSI Technology | |
| 19 | First Highly Stacked Ge0.95Si0.05 nGAAFETs with Record ION = 110 μA (4100 μA/μm) at VOV=VDS=0.5V and High Gm,max = 340 μS (13000 μS/μm) at VDS=0.5V by Wet Etching | Yi-Chun Liu, Chien-Te Tu, Chung-En Tsai, Yu-Rui Chen, Jyun-Yan Chen, Sun-Rong Jan, Bo-Wei Huang, Shee-Jier Chueh, Chia-Jung Tsen, and C. W. Liu (劉致為) | 2021 Symposium on VLSI Technology | |
| 20 | First Demonstration of Multi-VT Stacked Ge0.87Sn0.13 Nanosheets by Dipole-Controlled ALD WNxCy Work Function Metal with Low Resistivity and Thermal Budget ≤ 400 °C | Chung-En Tsai, Yu-Rui Chen, Chien-Te Tu, Yi-Chun Liu, Jyun-Yan Chen, and C. W. Liu (劉致為) | 2021 Symposium on VLSI Technology | |
| 21 | First Demonstration of Uniform 4-Stacked Ge0.9Sn0.1 Nanosheets with Record ION=78mA at VOV=VDS= -0.5V and Low Noise Using Double Ge0.95Sn0.05 Caps, Dry Etch, Low Channel Doping, and High S/D Doping | Yu-Shiang Huang, Chung-En Tsai, Chien-Te Tu, Jyun-Yan Chen, Hung-Yu Ye, Fang-Liang Lu, and C. W. Liu (劉致為) | 2020 IEEE International Electron Devices Meeting (IEDM) | |
| 22 | High On-Current 2D nFET of 390 μA/μm at VDS = 1V using Monolayer CVD MoS2 without Intentional Doping | Ang-Sheng Chou, Pin-Chun Shen, Chao-Ching Cheng, Li-Syuan Lu, Wei-Chen Chueh, Ming-Yang Li, Gregory Pitner, Wen-Hao Chang, Chih-I Wu (吳志毅), Jing Kong, Lain-Jong Li, and H.-S. Philip Wong | 2020 Symposium on VLSI Technology | |
| 23 | First Demonstration of 4-Stacked Ge0.915Sn0.085 Wide Nanosheets by Highly Selective Isotropic Dry Etching with High S/D Doping and Undoped Channels | Yu-Shiang Huang, Fang-Liang Lu, Chien-Te Tu, Jyun-Yan Chen, Chung-En Tsai, Hung-Yu Ye, Yi-Chun Liu and C. W. Liu (劉致為) | 2020 Symposium on VLSI Technology | |
| 24 | Record Low Contact Resistivity to Ge:B (8.1x10-10Ω-cm2) and GeSn:B (4.1x10-10Ω-cm2) with Optimized [B] and [Sn] by In-situ CVD Doping | Fang-Liang Lu, Yi-Chun Liu, Chung-En Tsai, Hung-Yu Ye, and C. W. Liu (劉致為) | 2020 Symposium on VLSI Technology | |
| 25 | Interpretable Neural Network to Model and to Reduce Self-Heating of FinFET Circuitry | Chia-Che Chung, Hsin-Cheng Lin, H. H. Lin, W. K. Wan, M.-T. Yang, and C. W. Liu (劉致為) | 2020 Symposium on VLSI Technology | |
| 26 | Bi-directional Sub-60mV/dec, Hysteresis-Free, Reducing Onset Voltage and High Speed Response of Ferroelectric-AntiFerroelectric Hf0.25Zr0.75O2 Negative Capacitance FETs | M. H. Lee (李敏鴻), K.-T. Chen, C.-Y. Liao, G.-Y. Siang, C. Lo, H.-Y. Chen, Y.-J. Tseng, C.-Y. Chueh, C. Chang, Y.-Y. Lin, Y.-J. Yang, F.-C. Hsieh, S. T. Chang (張書通), M.-H. Liao, K.-S. Li, and C. W. Liu (劉致為) | 2019 IEEE International Electron Devices Meeting (IEDM) | |
| 27 | First Vertically Stacked Tensily Strained Ge0.98Si0.02 nGAAFETs with No Parasitic Channel and LG = 40 nm Featuring Record ION = 48 mA at VOV=VDS=0.5V and Record Gm,max (mS/m)/SSSAT(mV/dec) = 8.3 at VDS=0.5V | Chien-Te Tu, Yu-Shiang Huang, Fang-Liang Lu, Hsiao-Hsuan Liu, Chung-Yi Lin, Yi-Chun Liu, and C. W. Liu (劉致為) | 2019 IEEE International Electron Devices Meeting (IEDM) | |
| 28 | First Stacked Ge0.88Sn0.12 pGAAFETs with Cap, LG=40nm, Compressive Strain of 3.3%, and High S/D Doping by CVD Epitaxy Featuring Record ION of 58mA at VOV=VDS= -0.5V, Record Gm,max of 172mS at VDS= -0.5V, and Low Noise | Yu-Shiang Huang, Chung-En Tsai, Chien-Te Tu, Hung-Yu Ye, Yi-Chun Liu, Fang-Liang Lu, and C. W. Liu (劉致為) | 2019 IEEE International Electron Devices Meeting (IEDM) | |
| 29 | First Vertically Stacked, Compressively Strained, and Triangular Ge0.91Sn0.09 pGAAFETs with High ION of 19.3uA at VOV=VDS=-0.5V, Gm of 50.2uS at VDS=-0.5V and Low SSlin of 84mV/dec by CVD Epitaxy and Orientation Dependent Etching | Yu-Shiang Huang, Hung-Yu Ye, Fang-Liang Lu, Yi-Chun Liu, Chien-Te Tu, Chung-Yi Lin, Shih-Ya Lin, Sun-Rong Jan, and C. W. Liu (劉致為) | 2019 Symposium on VLSI Technology | |
| 30 | Record Low Contact Resistivity (4.4x10-10Ω-cm2) to Ge Using In-situ B and Sn Incorporation by CVD With Low Thermal Budget (≤400℃) and Without Ga | Fang-Liang Lu, Chung-En Tsai, Chih-Hsiung Huang, Hung-Yu Ye, Shih-Ya Lin, and C. W. Liu (劉致為) | 2019 Symposium on VLSI Technology | |